** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1089) Only one discrete range allowed in slice name of "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(61): (vcom-1136) Unknown identifier "std_logic_2d".
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(95): (vcom-1141) Identifier "lpm_mux" does not identify a component declaration.
** Error: C:/Modeltech_6.1f/altera/src/liu_fpga12-18FIANAL/lpm_mux0.vhd(110): VHDL Compiler exiting
出错的程序是lpm_mux_component : lpm_mux和SIGNAL sub_wire4 : STD_LOGIC_2D (1 DOWNTO 0, 11 DOWNTO 0);这两行,该怎么改啊