library ieee;
use ieee.std_logic_1164.all;
entity when_else is
port ( s0,s1 : in bit;
a,b,c,d : in std_logic;
y : out std_logic);
end;
architecture bhv of when_else is
begin
process(s0,s1)
begin
y<=a when s0<='0' and s1<='0' else
b when s0<='0' and s1<='1' else
c when s0<='1' and s1<='0' else
d;
end process;
end bhv;
Error (10500): VHDL syntax error at if_then.vhd(5) near text "port"; expecting "is" æ¥éæ¯è¿ä¸ª
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